1. Field of the Invention
This invention relates generally to error correction, and more particularly to providing dynamically configurable multi level error correction hardware.
2. Description of the Related Art
As use of electronic data continues to increase, so do requirements for data storage reliability. Memory devices often experience a physical change that results in changes in its logical binary state, leading to erroneous data values being stored. To protect against such occurrences, electronic data systems typically incorporate error detection and correction schemes. In some schemes, the presence of an error can be detected, but not rectified, while other schemes allow for the automatic correction of certain errors. These schemes are often referred to as Error Correcting Codes (ECC).
ECC is common in data storage, such as magnetic disk storage, magnetic tape storage, and other non-volatile memory storage that stores data when power is disconnected from the system, such as Phase-change memory (PCM) or Flash memory. For example, when using a non-volatile memory such as Flash memory, ECC data often is stored in the memory along with the actual user data.
FIG. 1 is an illustration showing a typical prior art non-volatile memory arrangement 100 utilizing ECC data for data reliability checking. As illustrated in FIG. 1, a non-volatile memory 100 generally comprises a plurality of memory blocks 102, which generally is the smallest portion of memory that can be erased. Each memory block 102 generally comprises a fixed plurality of pages 104, which is the smallest size element that can be written or read from the non-volatile memory 100. Each page 104 typically is logically divided into two areas: a main area 106 and a spare area 108. It is in the spare area 108 where typical non-volatile memory systems store ECC data, such as the ECC check bits 110 illustrated in FIG. 1.
In general, prior art data storage devices, such as the non-volatile memory device illustrated in FIG. 1, are designed to use a fixed level of error correction and detection. For example, based on the reliability of the particular storage device and the desired level of data reliability needed, a fixed level of error correction and detection is used. Generally, higher levels of error correction and detection require more error detection data to be stored. For example, in FIG. 1, the higher the level of error correction and detection utilized, the more ECC check bits 110 are needed. This number is then set and fixed into the system design.
However, instances occur wherein the actual memory hardware may change, for example, when a Flash device is dynamically removed or added to a system. In such cases, the level of level of error correction and detection needed may change. For example, if more reliable memory is added to the system, the level of error correction and detection will be lower. Conversely, if less reliable memory is added to the system, the level of error correction and detection will be higher. Moreover, different hardware may have the ability to store less ECC data than is currently being utilized by the system. In such cases, it can be difficult or impossible to continue with the same level of error correction and detection because the required storage space for the ECC data may not be available. Unfortunately, conventional systems are unable to accommodate these circumstances because the level of error correction and detection is fixed when the system is designed.
In view of the foregoing, there is a need for systems and methods that have the ability to accommodate varying levels of error correction and detection dynamically during system operation. Moreover, to avoid wasted space and costs, such systems and methods should not require extra hardware that is never utilized in the system.